ASIC Verification Engineer
About The Position
Chain Reaction is a fast-growing startup developing cutting-edge hardware infrastructure for blockchain and cloud-privacy applications.
Our team takes products from ASIC definition, planning, and implementation all the way through production and deployment in multi-ASIC operational systems.
With a multidisciplinary team boasting decades of experience in developing and manufacturing high-end ASIC products, we set the highest standards for performance, efficiency, and quality.
Position Overview
We are looking for a talented VLSI Verification Engineer to join our team.
In this role, you will work on verifying complex ASIC designs, and collaborating with cross-functional teams to ensure silicon success.
You will define and implement verification strategies, debug failures, and contribute to the quality of our next-generation products.
Key Responsibilities
- Define verification plans and environment micro-architecture
- Implement UVM-based verification environments
- Debug and analyze failures at various stages of verification
- Develop coverage models and metrics to assess design readiness
- Support cross-functional teams (Analog, Backend, Production, etc.) on verification-related challenges
Requirements
- B.Sc. in Electrical Engineering or related field
- 0-4 years of experience in VLSI verification
- Experience with SystemVerilog or Specman (UVM is a plus)
Preferred Qualifications
Experience in any of the following is a plus
- Formal or Functional Verification tools
- FPGA design verification
- Mixed-signal verification
- Scripting & automation for verification flows